Design of Clock Synchronizers and Frequency Synthesizers
博士 === 國立臺灣大學 === 電機工程學研究所 === 88 === This thesis describes highly integrated phase-locked loops (PLLs) and delay-locked loops (DLLs) with advanced standard submicron CMOS technology to solve the problems of clock skew and frequency synthesis. It is divided into three parts. The first par...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/13735577581604174991 |