| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === In this thesis, a digital signal processor that is designed for communication appli-cations
with a programmable correlator array architecture is introduced. The pro-grammable
correlator can be easily configured as a chip match filter, code group
detector, scrambling code detector, and RAKE receiver. It also has low power
consideration.
The architecture and instruction set of the proposed DSP (CDSP) makes it
has good performance at Viterbi algorithm and complex arithmetic operations for
some wireless communication standards such as GSM and IS-95. According to
the performance evaulation results, the suggested DSP core outperforms other
DSPs in terms of several operations normally used in wireless communication.
The chip was implemented in a hybrid design method where the critical path was
full-custom designed and the other parts are cell-based using a 0.35um 1P4M
cell-library.
We believe that the suggested correlator array architecture and digital signal
processor are useful for future 3G mobile terminal design.
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