Parallel Logic Simulation for VLSI Verfication
博士 === 國立臺灣大學 === 資訊工程學研究所 === 88 === As the complexity of digital design continuously increasing, logic simulation becomes a crucial verification task in VLSI design. Traditional parallel logic simulation suffers from synchronization constraint and high data transmission rate. In this thesis, we wi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/56617362301746351724 |