FPGA Realization of the Viterbi Decoder for HDSL2 Systems

• Main Authors: Feng Lo, 羅鋒
• Other Authors: An-Yeu Wu
• Format: Others
• Language: en_US
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/71518173309172602090

碩士 === 國立中央大學 === 電機工程研究所 === 88 === High bit rate Digital Subscriber Line-2nd Generation (HDSL2) has been considered to make T1 more cost-efficient. HDSL2 delivers full-duplex T1 payload over one copper pair, and it offers a reach of 12,000 feet per span that is much over traditional T1 delivery. The Trellis-Coded Modulation (TCM) that consists of Pulse Amplitude Modulation (PAM) and the convolutional code is adopted as the line code scheme. In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device.