FPGA Realization of the Viterbi Decoder for HDSL2 Systems
碩士 === 國立中央大學 === 電機工程研究所 === 88 === High bit rate Digital Subscriber Line-2nd Generation (HDSL2) has been considered to make T1 more cost-efficient. HDSL2 delivers full-duplex T1 payload over one copper pair, and it offers a reach of 12,000 feet per span that is much over traditional T1...
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/71518173309172602090 |