A 3V 9Gbps CMOS Multiplexer
碩士 === 國立交通大學 === 電子工程系 === 88 === This thesis described the design of a 3V CMOS Multiplexer that transmits 9 gigabit per second, which is composed of a frequency multiplier path, an 18 to 1 multiplexer, an 18 phase phase-lock-loop (PLL) clock generator. This CMOS Multiplexer is applied t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51038875344333470981 |