Jitter Analysis Due to Noise in the Phase-Locked Loop Circuits

Jitter Analysis Due to Noise in the Phase-Locked Loop Circuits

碩士 === 國立交通大學 === 電子工程系 === 88 === The Phase-Locked Loop circuit is usually employed as a clock generator in the digital or communication system. Its stability determines the limiting stability of system. In this thesis ,we propose a behavioral noise model for which the transfer function...

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Bibliographic Details
Main Authors:	Ching-Tsan Lee, 李敬贊
Other Authors:	Chung-Len Lee
Format:	Others
Language:	zh-TW
Published:	2000
Online Access:	http://ndltd.ncl.edu.tw/handle/57009169064196771229

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