Jitter Analysis Due to Noise in the Phase-Locked Loop Circuits
碩士 === 國立交通大學 === 電子工程系 === 88 === The Phase-Locked Loop circuit is usually employed as a clock generator in the digital or communication system. Its stability determines the limiting stability of system. In this thesis ,we propose a behavioral noise model for which the transfer function...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57009169064196771229 |