Jitter Analysis Due to Noise in the Phase-Locked Loop Circuits
碩士 === 國立交通大學 === 電子工程系 === 88 === The Phase-Locked Loop circuit is usually employed as a clock generator in the digital or communication system. Its stability determines the limiting stability of system. In this thesis ,we propose a behavioral noise model for which the transfer function...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/57009169064196771229 |
| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 88 === The Phase-Locked Loop circuit is usually employed as a clock generator in the digital or communication system. Its stability determines the limiting stability of system. In this thesis ,we propose a behavioral noise model for which the transfer function was deduces by mathematics tools (MatLab). Based on this model , the power supply noises injected from each sub-block of the PLL circuit were analyzed to see how they affect the PLL output frequency ( jitter) . A practical PLL circuit was designed by using the TSMC 0.6u CMOS process. For this circuit ,noise of various frequencies were injected to each sub-block of the PLL .The spice simulation results were compared with those derived from the model .It showed that the spice experimental result agree with those derived from the model .This demonstrates that our proposed mathematical model can be used to analyze noise of the PLL circuit, enabling saving of much computation time.
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