Construction Schemes for Fault Tolerant Hamiltonian Graphs
博士 === 國立交通大學 === 資訊科學系 === 88 === An interconnection network connects the processors of the parallel computer. Its architecture can be represented as a graph in which the nodes correspond to the processors and the edges to the communication links....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/18239830827400922717 |