A 14-bit Recirculating A/D converter with 60MHz Clock Rate
碩士 === 國立成功大學 === 電機工程學系 === 88 === In this thesis, digital error correction algorithms and capacitor mismatch error reduction algorithms are discussed and compared. Then, the reduced interstage gain digital error correction and the commutating feedback-capacitor switching (CFCS) algorithm are ch...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23065888903299865311 |