1.5V 900MHz CMOS Phase-Locked Loop
碩士 === 國立中興大學 === 電機工程學系 === 88 === This thesis describes a 1.5 V 900 MHz CMOS phase-locked loop (PLL), which is composed of a phase/frequency detector (PFD), a charge-pump (CP), a low-pass filter (LF), a voltage-controlled oscillator (VCO) and a multi-scale frequency divider (FD). This P...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/41050153157710986351 |