Design of an ATM Chip with IRR Scheduling
碩士 === 國立中正大學 === 電機工程研究所 === 88 === ATM network is an ideal broadband network platform rewards to work for, this thesis proposes a practical hardware architecture that integrates ATM layer and ATM adaptation layer functions - AAL5 of ATM network protocol. It also supports multiple I/O ports and has...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04131212152874267037 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 88 === ATM network is an ideal broadband network platform rewards to work for, this thesis proposes a practical hardware architecture that integrates ATM layer and ATM adaptation layer functions - AAL5 of ATM network protocol. It also supports multiple I/O ports and has the ability of transmission、receiving、switching、segmentation and reassembly. The linked-list method is used to manage the information that is stored in a shared memory.
Quality of Service (QoS) is an important service of ATM network. The Interleaved Round-Robin (IRR) scheduling algorithm is a simple method that can reduce transmission delay and jitter efficiently. This thesis also implements an IRR circuit in the chip but it will be implemented and verified independently. After post-layout simulation by TimeMill, the IRR chip can operates correctly under 33MHz operating frequency.
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