Functional Slack Time Computation via Non-primitive Path Detection
碩士 === 國立中正大學 === 資訊工程研究所 === 88 === Abstract Given that the power dissipated by a gate is directly proportional to its load, reducing that load (down sizing) leads to a reduction of the power consumption as well as a reduction of the chip area. Downsizing gates can reduce power/area...
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| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88293973554132135273 |