Modeling of Gate-Induced Drain Leakage Currents of MOSFETs

• Main Authors: Hao-Hsun Lin, 林浩勳
• Other Authors: Sheng-Lyang Jang
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/67665048667196830973

碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === In this thesis we present compact drain leakage current models for submicron surface-channel nMOSFETs, buried-channel MOSFETs and silicon-on-insulator pMOSFETs. The analytical and physics-based models were developed using a quasi-two dimensional approach, in which the longitudinal and vertical surface channel electric fields can be calculated. The effective gate-overlap drain region for band-to-band tunneling drain leakage current can be calculated, and it is a function of gate and drain biases. The drain leakage current can be accurately calculated as a function of drain and gate biases, channel and drain doping concentrations. These drain leakage curren models in conjunction with our previous published subthreshold and above threshold models form a concrete drain current model for MOSFET operation in off and on states.