A Study of Trap-Assisted Tunneling Gate Current in PMOSFET's with Sub-3nm Gate Oxide
碩士 === 國立清華大學 === 電機工程學系 === 87 === In order to increase performance and reduce production cost, CMOS scaling is an inevitable trend. As the channel length decreases, thin oxide is required to retain the gate controllability. The advantages of ultra-thin oxide devices include large channe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90020135281191920546 |