| Summary: | 碩士 === 國立清華大學 === 工業工程與工程管理學系 === 87 === The semiconductor manufacturing involves extremely complex processes and high cost. Any error occurred in the process may induce serious damage to the enterprise. Therefore, how to improve the yield is the goal that each semiconductor factory is engaged to accomplish. However, the existing methods analyzing the process are independent instead of being well-integrated. Meanwhile, the diagnosis experience of engineers is difficult to accumulate in a systematic way.
For the reason, this research takes failure analysis as an example to demonstrate a methodology that can help develop an integrated failure analysis system which will trigger analysis activities automatically based on the results of other activities. At first, the system applies SADT/IDEF0 to illustrate functions, relationships and data flow of the failure analysis system in a static nature. The control flow is then abstracted and transformed into dynamic control logic represented by Petri nets. Using Petri nets as an interface between IDEF0 model and system implementation, problems about constructing the failure analysis system can be reduced.
Through the verification of system implementation, the methodology is proved to work practicably. Following the steps of this methodology, it is possible to develop a system which integrates more engineering data analysis functions together to reach the goal of yield enhancement.
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