| Summary: | 碩士 === 國立中央大學 === 電機工程研究所 === 87 === The operation frequency of VLSI systems has increased as VLSI process technology has advanced. To satisfy the speed requirements, reducing skew between an external clock and an on-chip clock is the most effective way. The delay-locked loop (DLL) is placed on a design to decrease both skew and jitter of clock used in the internal chip.
In this thesis, a DLL based upon self-biased techniques is proposed. The DLL design achieves process technology independence, broad operation frequency range, low tracking jitter and phase offset. In addition, we develop a new structure for array DLL that is a 3-D architecture. It can operate in higher speed and ideally have smaller jitter than the traditional 2-D array DLL. According to the improvement version of 2-D array DLL, we develop an application for the simultaneous switching outputs (SSO). Using the polyphase outputs of the voltage controlled delay line (VCDL) of the array DLL to avoid the several output signals simultaneous be triggered and can effectively reduce the SSO effect.
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