The Design and Application of Self-Biased Delay-Locked Loop
碩士 === 國立中央大學 === 電機工程研究所 === 87 === The operation frequency of VLSI systems has increased as VLSI process technology has advanced. To satisfy the speed requirements, reducing skew between an external clock and an on-chip clock is the most effective way. The delay-locked loop (DLL) is pla...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96903851568704913520 |