Two Level Trace Cache

碩士 === 國立交通大學 === 資訊工程系 === 87 === We proposed a hierarchical trace cache mechanism to increase the capacity of trace cache. This mechanism, called two level trace cache, employs both the concept of memory hierarchy and trace cache technique. By evaluating read and write policies of trace...

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Bibliographic Details
Main Authors: Bor-Naen Chen, 陳柏年
Other Authors: Chung-Ping Chung
Format: Others
Language:en_US
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/43965587593267356304