An Analytical Delay Model for Read Operation on Dynamic Random Access Memory Bit Lines

• Main Authors: Chia-Hsiang Shih, 施家祥
• Other Authors: Hongchin Lin
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/85749102405893791140

碩士 === 國立中興大學 === 電機工程學系 === 87 === As VLSI circuits migrate to high density, DRAM device technology advances to the deep sub-micron range. The small devices can meet the requirement of the high-speed and high-density, but many other problems degrade circuit performance or even invalidate the original design, especially the interconnect problem influencing the circuit performance is getting more seriously. In general, the circuit designers estimating the delay of interconnect employ the conventional discrete R and C components. Since the numbers of R and C are limited to small numbers, the accuracy is becoming unsatisfied. The interconnect delay occupies the larger percentage of the total delay, so the accuracy of circuit simulation is degraded as the devices are getting smaller, it is necessary to develop a new RC delay model to meet the trend. The purpose of this thesis is to develop a new analytical delay model for read operation on DRAM bit lines, the circuit designers can use the model to compute the variation of output voltage accurately and quickly on the DRAM bit line with the RC delay effect. The new model was compared with the numerical analysis of the HSPICE (circuit simulation software) and TMA (device/process simulation software). The accuracy between the new model and SPICE simulation / TMA simulation is excellent. It is much more accurate than the conventional discrete RC delay model. In addition, the method to calculate the delay for ramped voltages on the word line was proposed with excellent results, too. Finally, a 0.18μm DRAM device using TMA was simulated to further verify the accuracy of the derived model. In order to compare with the experimental data on a real chip, a test circuit for DRAM bit line delay is fabricating in Winbond Electronic Inc. Our group will continue to complete the measurement and compare with the derived delay model to certify the accuracy of this new analytical model.