Synthesis for Multiple Input Wire Replacement of a Gate for Wiring Consideration
碩士 === 國立中正大學 === 資訊工程研究所 === 87 === Traditionally, interconnect or layout synthesis takes a fixed net list and attempts to optimize the interconnections from the given net list. However, because the wire delay/area has become a dominating factor in system performance of VLSI circuits, it...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/11259357596685081614 |