A mixed-level power estimator forCMOS circuits using pattern compaction techniques

A mixed-level power estimator forCMOS circuits using pattern compaction techniques

碩士 === 國立交通大學 === 電子工程學系電子研究所 === 86

Bibliographic Details
Main Author:	許文亮
Other Authors:	沈文仁
Format:	Others
Language:	en_US
Published:	1998
Online Access:	http://ndltd.ncl.edu.tw/handle/mc88xh

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