A mixed-level power estimator forCMOS circuits using pattern compaction techniques

Similar Items

• Power estimation for CMOS VLSI circuits
  by: Ruey Wen Tsay, et al.
  Published: (1993)
• Circuit Level Techniques for Power and Reliability Optimization of CMOS Logic
  by: Diril, Abdulkadir Utku
  Published: (2005)
• Power estimation by transition density in CMOS circuits
  by: Tai-Chien Liu, et al.
  Published: (1994)
• Techniques for Low Power Analog, Digital and Mixed Signal CMOS Integrated Circuit Design
  by: Zhang, Chuang
  Published: (2005)
• A Refined Mixed-Level Power Estimation Approach For CMOS Logic Design
  by: Chi-Chang Lu, et al.
  Published: (2001)