A mixed-level power estimator forCMOS circuits using pattern compaction techniques

碩士 === 國立交通大學 === 電子工程學系電子研究所 === 86

Bibliographic Details
Main Author:	許文亮
Other Authors:	沈文仁
Format:	Others
Language:	en_US
Published:	1998
Online Access:	http://ndltd.ncl.edu.tw/handle/mc88xh

id	ndltd-TW-086NCTU0428026
record_format	oai_dc
spelling	ndltd-TW-086NCTU04280262019-05-16T00:44:35Z http://ndltd.ncl.edu.tw/handle/mc88xh A mixed-level power estimator forCMOS circuits using pattern compaction techniques 一個利用圖樣壓縮技術的混合層級功率估測器許文亮碩士國立交通大學電子工程學系電子研究所 86 沈文仁 1998 學位論文 ; thesis 56 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子工程學系電子研究所 === 86
author2	沈文仁
author_facet	沈文仁許文亮
author	許文亮
spellingShingle	許文亮 A mixed-level power estimator forCMOS circuits using pattern compaction techniques
author_sort	許文亮
title	A mixed-level power estimator forCMOS circuits using pattern compaction techniques
title_short	A mixed-level power estimator forCMOS circuits using pattern compaction techniques
title_full	A mixed-level power estimator forCMOS circuits using pattern compaction techniques
title_fullStr	A mixed-level power estimator forCMOS circuits using pattern compaction techniques
title_full_unstemmed	A mixed-level power estimator forCMOS circuits using pattern compaction techniques
title_sort	mixed-level power estimator forcmos circuits using pattern compaction techniques
publishDate	1998
url	http://ndltd.ncl.edu.tw/handle/mc88xh
work_keys_str_mv	AT xǔwénliàng amixedlevelpowerestimatorforcmoscircuitsusingpatterncompactiontechniques AT xǔwénliàng yīgèlìyòngtúyàngyāsuōjìshùdehùnhécéngjígōnglǜgūcèqì AT xǔwénliàng mixedlevelpowerestimatorforcmoscircuitsusingpatterncompactiontechniques
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A mixed-level power estimator forCMOS circuits using pattern compaction techniques

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