Improving Branch Target Prediction with Register References
碩士 === 國立交通大學 === 資訊工程學系 === 86 === Branch insrtuctions are always the performance bottleneck of modern pipelined superscalar processors.Branch instructions can interrupt the steady flow of instruction stream in the pipeline.To resolve th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/97884368331079169018 |