| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 86 === BIFEST(A Built-in Intermediate Fault Effect Sensing and Test
GenerationSystem for CMOS Bridging Faults)是一個處理橋式錯誤之自
動測試向量產生（Auto Test Pattern Generation or ATPG）系統，其主
要功能在於利用邏輯測試方法及內建式中間電壓值測試法（Built-in
IntermediateVoltage Testing or BIVT）去偵測橋式錯誤；BIFEST之邏
輯測試法是一傳統之ATPG系統，即使用相似於PODEM與PPSFP之方式完成的
，而BIVT方法是針對剩餘未被邏輯測試法偵測到之橋式錯誤，其會產生中
間電壓者，使用一內建式中間電壓感測器（Built-in Intermediate
Voltage Sensors or BIVS）去偵測。此篇論文在已有的BIFEST系統下，
分析各種剩餘無法使用BIFEST之邏輯測試法偵測之橋式錯誤，探討造成其
未能被測到的原因，以及討論具有哪些特性之橋式錯誤無法使用BIFEST之
BIVT方法偵測到；最後我們發現大部分是因電路之特性，而致使許多錯誤
無法使用BIFEST之邏輯測試法偵測到，唯有橋式錯誤型式是發生在一邏輯
閘之兩輸入情況，因系統採用悲觀的邏輯閘臨界電壓模型，而造成錯誤效
應易成為中間電壓值（介於邏輯1與邏輯0之間），及此種橋式錯誤之錯誤
涵蓋率過低；在分析完BIVT程序後，我們發現無法使用BIVT方法偵測到之
橋式錯誤，其無法產生中間值電壓。另外在BIFEST系統中，其邏輯閘臨界
電壓判定模型並不完善，故我們發展了一套改良版之邏輯閘臨界電壓判定
模型，其有較高的正確性且可涵蓋更多情況，最後我們將BIFEST之邏輯閘
臨界電壓判定模型代換成新的模型，如預期的，其結果較正確且邏輯測試
程序之錯誤涵蓋率會提升。
BIFEST (A Built-in Intermediate Fault Effect sensing and Test
Generation System for CMOS Bridging Faults) is an ATPG
(Automatic Test Pattern Generation) system for bridging faults.
The BIFEST system combines logic testing method and Built-in
Intermediate Voltage Testing (BIVT) method to detect bridging
faults. The logic testing method of BIFEST is a conventional
ATPG process that employs PODEM-like and PPSFP-based methods.
The BIVT method is developed for remaining faults after logic
testing. If the emaining bridging faults result in intermediate
voltage then they are dealt with by special circuits called
built-in intermediate voltage sensors (BIVSs).In this thesis, we
analyze remaining bridging faults that cannot be detected by
logic testing of BIFEST and discuss the reasons. We also discuss
the properties of faults that cannot be detected by the BIVT
method. After analyzing, we find that causation that makes
bridging undetectable by logic testing of BIFEST is mostly due
to circuit characteristics. For the case that when the bridging
fault ype is between two inputs of a logic gate(In2BF), the
fault effects become intermediate voltage easily and the fault
coverage of In2BF is lower because BIFEST system uses a
pessimistic model of gate threshold. After analyzed the BIVT
method, we find that the bridging faults that are undetectable
by BIVT cannot produce intermediate voltage at bridging sites.In
BIFEST system, the logic gate threshold determination method is
not good, so we improve the original model to get a new one. The
new logic gate threshold determination model is more accurate
and it covers more conditions. Then we replace the original gate
threshold determination model with the new one. As expected, we
obtain the higher accuracy and fault coverage after logic
testing in BIFEST system.
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