Bridging Fault Analysis and Logic Gate Threshold Voltage Determination
碩士 === 國立成功大學 === 電機工程學系 === 86 === BIFEST(A Built-in Intermediate Fault Effect Sensing and Test GenerationSystem for CMOS Bridging Faults)是一個處理橋式錯誤之自 動測試向量產生（Auto Test Pattern Generation or ATPG）系統，其主 要功能在於利用邏輯測試方法及內建式中間電壓值測試法（Built-in...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24839279878536979046 |