Exploring New Micro-architecture for Improving the Performance of a Superscalar Microprocessor

• Main Authors: Akida Wu, 巫秋田
• Other Authors: Chen, Chung-Ho
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/02025690233176931891

碩士 === 國立雲林科技大學 === 電子與資訊工程技術研究所 === 85 === 　　We have developed an enhanced DLX-based superscalar system simulator to explore new micro-architectures for improving the performance of a superscalar processor. In this simulator, we design a KNL-cache model for both instruction and data caches and a burst transfer memory model to construct a more realistic environment for performance evaluation In this thesis we compare the performance contribution from each part of the mechanisms built in the Superscalar-DLX processor. 　　We proposed two new micro-architectures used for superscalar microprocessors. One is a load prediction mechanism using a base and offset cache. The other is a high performance load/store unit design. For the first approach, loading data using a predicted target address is able to achieve 13%∼21.7% performance improvement on average. High performance load/store unit design reduces the load-stalls by increasing parallelism between load and store instions and provides about 41.9%∼69.4% performance improvement. 　　For load-prediction, we proposed a configuration of using a 128 entry direct-mapped BOC with 2 forwarding paths and adders. This configuration can achieve 9∼18% performance improvement on average For load/store unit design, our approach (bypassload+strc+fsac+scsl) is able to achieve 36.8%∼46.8% performance improvement based on a load/store issue scheme that is used widely by most of the current superscalar processors. We also find that if we provide two load/store units with load bypassing store capability, we can obtain a significant performance enhancement.