Low Power Circuit in Bipartition-Codec Architecture
碩士 === 國立臺灣大學 === 資訊工程學系 === 85 === The precomputation architecture and gated-clock implementation can effectively reduce toggles in CMOS circuits to reduce power consumption by using a small dominant function to predict the logic output. When a small com...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/39872402500969245922 |