Post-Layout Performance Optimization Using Gate Sizing and Buffer Insertion
碩士 === 國立清華大學 === 資訊科學研究所 === 85 === In a deep sub-micron IC design, the wire delay becomes more and more significant and even dominant. During logic synthesis, the wire delay estimation is less accurate because of lack of physical design information. In this thesis, we integrate logic synthesis...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59178184288804228575 |