The Research of DRAM Circuit and New Memory Cell
碩士 === 國立中山大學 === 電機工程研究所 === 85 === A 4-Mb DRAM with 30ns RAS access time and fast accessing data operation, Nibble mode, has been designed. We use three circuit design techniques that are bit line pairs pre-equalized, sense amplifiers drove by Full Vcc, and CSL turned on after WL, to improve...
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| Format: | Others |
| Language: | zh-TW |
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1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/11304061813035745106 |