| Summary: | 碩士 === 國立交通大學 === 電子工程學系 === 85 === Previous study used CVD oxide/thermal SiO2 stacked dielectric
for MOS gate material with the advantages of high resistance to
process induced defect density. Ta2O5/thermal SiO2 stacked gate
dielectrics have been explored in this thesis. Ta2O5 was used
because of its high dielectric constant and N2O-grown oxide was
used due to the nitrogen incorporation in the SiO2/Si interface
which leads to a high device reliability. The current-voltage,
capacitance-voltage characteristics have been investigated as
wellLow-temperature plasma annealing was investigated to reduce
the CVD Ta2O5 leakage current. The effect of ambient, pressure,
power, and bottom electrode were examined. It was found that
annealing in low pressure and in N2O are effective in reducing
leakage current but will degrade the capacitance performance.
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