| Summary: | 碩士 === 國立交通大學 === 電子工程學系 === 85 === This thesis describes the design of a 2~V, 110 MHz CMOS
limiting amplifier, which consists of a gain stage, a offset
canceling circuit, a received signal strength indicator(
RSSI), and a winding-swing constant-transconductance bias
circuit.
The key component is the gain stage which cascode eight the same
gain cells, called core cell. Under the other
circuits' help, every transistor in the core cell can always
keep constant transconductance (gm). We use this
character to decrease the phase error, which is the most
important for our total performance.
The offset canceling circuit used in the gain stage cancel the
offset of the difference output of every core cell. If
there is one offset in the core cell input/output node, the
gain stage won't work correctly.
The received signal strength indicator record the change of
signal strength. RSSI is implemented by analog signal
usually, but we use a one bit digital signal to do
this. It is because our power supply is only 2~V. If we use
analog signal , the reasonable range is very narrow. We need
use a digital filer to analysesthe digital output.
The limiting amplifier has been implemented with the TSMC 0.6~$
\mu$m SPDM CMOS technology. Total chip size is $1500~um \times
1200~\mu\mbox{m}^2$, including pads and operate from a
single 2~V supply. the center frequency is 110 MHz and total
power consumption is 23 mW.
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