A 2V , 110MHz CMOS limiting amplifier
碩士 === 國立交通大學 === 電子工程學系 === 85 === This thesis describes the design of a 2~V, 110 MHz CMOS limiting amplifier, which consists of a gain stage, a offset canceling circuit, a received signal strength indicator( RSSI), and a windi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26644608797311719577 |