| Summary: | 博士 === 國立交通大學 === 電子工程學系 === 85 === This dissertation is divided into two parts. The former
investigates delay fault testing and the latter is dedicated to
distributed fault simulation.Concerning delay fault testing, a
new test methodology, oscillation ringtest, and its associated
testing circuit organization for digital circuitsare first
proposed. The generated test vectors can detect all the stuck-
atfaults, all the gate delay faults and part of path delay
faults. This method tries to find a set of sensitizable paths
to cover all the circuit lines. Aninverting feedback or
noninverting feedback is added to the path to form aring with
odd inversion parity. A test vector which sensitizes the
pathmakes this ring oscillate. The strategy of multiple
oscillation rings isadopted in this work to reduce the size of
test set. Next, a theoretical analysis to identify robust
untestable path delayfaults is presented. Reconvergence of
paths are classified into seven casesand the necessary condition
to robustly test path delay faults for each caseis deduced. The
proposed procedure is suitable for distributed processing
bycircuit partitioning to reduce the computation time and
required memory.Experimental results on ISCAS 85'' benchmark
circuits show that the robustuntestable faults occupy a high
percentage. Finally, a functional test pattern generation
scheme for obtaining highlyefficient robust tests for path delay
faults is presented. The scheme firstanalyzes independent
faults that can not be detected in a single pattern pairand then
distributes these independent faults into different groups.
Thisreduces the number of candidate faults that may be
simultaneously detected inthe same pattern pair. The proposed
scheme is coded in a vector processingmethodology to reduce
computation time and required memory. Experimentalresults
demonstrate that our method is fast and the generated pattern
pairsare very efficient in detecting path delay faults.
Concerning fault simulation, a two-phase fault simulation scheme
forsequential circuits is first proposed. In this fault
simulation, the faultfree simulation is first performed with few
patterns, and then the faultsimulation is performed with the
rest of patterns. Five cases of faultswhich result from two-
phase fault simulation are discussed in detail.Significant
speedup on simulation time can be obtained because this
faultsimulation approach can quickly drop Case 1 faults, which
are time-consumingfaults and would be considered to be
undetectable in the traditionalthree-value fault simulation but
are really detected in the exact faultsimulation. Based on
the concept of the two-phase fault simulation, distributed
faultsimulation by pattern partitioning for sequential circuits
is proposed. Thissimulation is done by making each distributed
machine perform fault-freesimulation with preceding patterns and
then perform fault simulation with itsown patterns. The fault
simulation is accelerated since the number ofpatterns needed to
be performed fault simulation for each machine is reducedby a
factor of n, the number of machines, and the faults detected by
anymachine are dropped through communication of the network. A
super-linearspeedup can be obtained because this method can also
remove the Case 1 faults.
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