Issues of the RISC Execution Core for a Superscalar CISC Microprocessor
碩士 === 國立交通大學 === 資訊工程學系 === 85 === Originally, Intel x86 processor is a scalar CISC processor, i.e. it can finish one x86 instruction per cycle at the most. Due to the inhibitive cost and the limitation of semiconductor process technology...
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| Format: | Others |
| Language: | zh-TW |
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1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/36939627583475659122 |