IC Design of Low Power Decimation Filter with Periodically Time-Varying Coefficients
碩士 === 國立成功大學 === 電機工程學系 === 85 === In this thesis, a decimation filter is designed for an audio Sigma-Dalta A/D Converter. The decimation filter has a downsampling rate of 64 and bandwidth of 20KHz. With a frontend lowpass filter, aliasing is cancelled to achieve high-quality audio signals. A...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06019252508690883643 |