Comparision of ADC Archiectures and Design and Analysis of 8-bit SAR ADC
碩士 === 中華大學 === 電機工程學系 === 85 === In this thesis, an 8-bit 500KS/sec A/D converter designed and analyzed, and is fabricated in a 0.5um CMOS process. The A/D converter was designed to have a sampling time of 2us at clock rate of 1MHz. The ADC was designed with Op-Amps which has the characterist...
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| Format: | Others |
| Language: | zh-TW |
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1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/24706430557173984858 |