| Summary: | 碩士 === 國立臺灣大學 === 電機工程研究所 === 84 === In this thesis, we have designed and implemented a decoder
chip that conforms completely with the POCSAG (Post Office
Code Standardization Advisory Group) specifications. This
decoder supports 512 bits/s and 1200 bits/s data rates. It
can be used for paging system, and is the heart component in
pagers nowadays . As a result, this POCSAG decoder can be
used in practice and has high commercial value. The
architecture of this decoder by utilizing top-down design
flow is presented. In the proposed architecture, the error
bits (no more than two) in each received codeword can be
corrected. In addition, the third error bit which occurs
on the even parity bit can also be detected. Moreover, by
analyzing and utilizing the characteristics of the POCSAG
signal format, the power consumption of RF module in the pager
receiving system can be effectively reduced. The physical
level design is implemented and verified using the
Verilog hardware description language. Finally, the chip
floorplan is generated using the standard cells from the
cell library provided by Computer and Communication
Research Laboratories. Concurrently, we also demonstrate that
the proposed architecture is easily developed and maintained by
top-down design flow.
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