Design and Implementation of a POCSAG Decoder for Pagers
碩士 === 國立臺灣大學 === 電機工程研究所 === 84 === In this thesis, we have designed and implemented a decoder chip that conforms completely with the POCSAG (Post Office Code Standardization Advisory Group) specifications. This decoder supports 512 bits/s and...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43227831197910298487 |