Low-Power VLSI Implementation of DLMS Adaptive FIR Filters
碩士 === 國立清華大學 === 電機工程研究所 === 84 === In this thesis, we present a pipelined bit-serial VLSI architecture for realizing an N-tap adaptive FIR filter using the delayed least mean square (DLMS) algorithm. The architecture consists of bit-serial systolic arrays for performing filtering/adaptation operat...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1996
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/83035509126640882305 |