A 2V, 110 MHz, 64-Phase CMOS PLL
碩士 === 國立交通大學 === 電子研究所 === 84 === This thesis described the design of a 2V 110 MHz 64-phase CMOS phase-lockedloop (PLL), which is to be used in a phase-magnitude vector modulator. The PLLis consisted of 64-phase voltage- controlled oscil...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88761206623586797851 |