Study of Post-Stress Gate Currents

• Main Authors: Chorng-Jye Sheu, 許重傑
• Other Authors: Sheng-Lyang Jang
• Format: Others
• Language: zh-TW
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/75902722127520201743

碩士 === 國立臺灣科技大學 === 工程技術研究所 === 83 === An efficient and accurate pseudo-two-dimensional simulation technique was developed to study the fresh and post-stress gate currents of MOSFETs. In the fresh case, we modified the lucky-electron concept by considering the image-force-induced barrier lowering at the silicon and metal system for charge carrier injection. The injection mechanism in n-MOSFETs was channel hot electron injection. In p-MOSFETs, we focused on the injection mechanism of drain avalanche hot carriers. In post-stress n-MOSFETs, the effects of hot-electron induced interface-traps on gate currents were taken into account. The interface states changed the channel electric field and increased the injection probability and gate currents. In post-stress p-MOSFETs, we presented a model dealing with the channel electric field distribution with the effect of oxide trapped charge and the gate currents. Our modified field model can explain the reduction of the channel electric field and the decrease of gate currents with increasing oxide trapped electron charge.