Submicron CMOS Latch-up and Substrate Bias Generators

• Main Authors: Yeh-Huei Jou, 周業輝
• Other Authors: Ming-Jer Chen
• Format: Others
• Language: en_US
• Online Access: http://ndltd.ncl.edu.tw/handle/77840219187218865145

碩士 === 國立交通大學 === 電子研究所 === 83 === The essential study of this thesis is on the submicron CMOS latch-up effect. We can draw a general understanding of the physical characteristics of latch-up, with an aim to raise the holding voltage for meeting the industrial requirements. Thus, we utilize the semiconductor device simulator MEDICI to analyze various configurations. Under the fixed process parameter, we change the epitaxial layer thickness, n+/p+ spacing, substrate bias...etc, in order to raise the holding voltage. Further, we separate the latch-up curve into the "three sub- regions/two points" based on the simulation results.Thus various physical parameters can be extracted for study and analysis. In the vicinity of holding point where the physical mechanism is like a p-i-n diode structure, we have derived a holding voltage model. On the other hand,by following the international standard latch-up test guidelines, we set up a latch-up test system and methodology. At the same time, we propose a design rule for latch-up robustness. In substrate bias generator, we utilize charge pumping principle, and design and fabricate a set of bias generator to support on chip a positive/negative bias. Applying it to the CMOS chip will raise the holding voltage efficiently.