Submicron CMOS Latch-up and Substrate Bias Generators
碩士 === 國立交通大學 === 電子研究所 === 83 === The essential study of this thesis is on the submicron CMOS latch-up effect. We can draw a general understanding of the physical characteristics of latch-up, with an aim to raise the holding voltage for me...
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| Format: | Others |
| Language: | en_US |
| Online Access: | http://ndltd.ncl.edu.tw/handle/77840219187218865145 |