A New Design Methodology for Deep-Submicrometer SOI MOSFET's

• Main Authors: Shih-Jian Lien, 連士進
• Other Authors: Ching-Yuan Wu
• Format: Others
• Language: en_US
• Published: 1995
• Online Access: http://ndltd.ncl.edu.tw/handle/21734550504899800137

碩士 === 國立交通大學 === 電子研究所 === 83 === This thesis presents a new design methodology for deep- submicrometer SOI MOSFET's using both 2-D numerical analysis and analytic models. In order to understand the complicate device physics underlying short-channel SOI MOSFET's, a threshold-voltage model based on quasi-2D analysis is used to analyze the effects of device structure and process parameters on the threshold voltage and the drain-induced barrier lowering of short-channel fully-depleted SOI MOSFET's. Moreover, a simple criterion is developed to identify fully- depleted and partially-depleted operations of a SOI MOSFET. In addition, the 2-D numerical analysis is used to verify the structure and process parameters on the potential distribution and the subthreshold I-V characteristics from which the drain- induced barrier lowering and the punch-through effects can be easily identified. Based on the developed new design methodology, a 0.1um channel-length SOI MOSFET is designed and its excellent I- V characteristics including subthreshold and turn-on I-V characteristics are demonstrated.