| Summary: | 碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis,we present two important hardware designs for
video image compression.One is motion estimation processor,the
other is CoDec VLSI chip. Full-search block-matching algorithm
(FSBMA) has been popularly used in the area of motion
estimation for video image compression.However,it is
computationally intensive.During the past,to improve the
performance,a novel two-dimensional SIMD-systolic architecture
has been derived for the FSBMA.Also, based on this architecture
and a 0.8um CMOS technology,a VLSI motion estimation chip has
been implemented and fabricated. Currently,with such a chip,a
high performance motion estimation processor has been developed.
Additionally,under the control of C program,this processor has
been combined with PC-486 through AT-bus interface.Experimental
results also have shown that the current design can compute
4000 motion vectors in one second. Quantization/Dequantization
and entropy coding/decoding are also widely used techniques for
video image compression.Combining them together,we propose a
Codec VLSI architecture for these operations.Currently,based on
a 0.8um SPDM CMOS technology,a VLSI chip has been implemented
for such architecture.The chip consists of 78912 transistors
and has a core size of 0.34 square centimeter.Testing results
have shown that this chip is functionally correct and can
complete one encoding process or decoding process for 8x8 block
in 105∼169 or 134∼198 clock cycles.
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