The Design of Motion Estimation Processor and CoDec VLSI Chip for Video Image Compression
碩士 === 國立臺灣科技大學 === 工程技術研究所 === 82 === In this thesis,we present two important hardware designs for video image compression.One is motion estimation processor,the other is CoDec VLSI chip. Full-search block-matching algorithm (FSBMA) has be...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1994
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/90459766717396372769 |