| Summary: | 碩士 === 國立清華大學 === 電機工程研究所 === 82 === In this thesis, we review IEEE Boundary Scan (BS) Std.
1149.1-1990 and Boundary Scan Description Lan- guage (BSDL),
and discuss boundary scan generation methodology. We develop a
CAD tool (BS-BIST generator) to automatically generate the
boundary scan circuitry. The user needs not know the standard
in detail. By use of the friendly graphical user interface, he
can execute it interactively. The tool implements the mandatory
BS instructions and architecture and some optional instructions
defined in the standard. After synthesizing the boundary scan
logic, the tool support a simulation environment to let the
user verify the functions. The design flow can be executed
iteratively until the result satisfies his goals. The tool can
also generate the BSDL file automatically. We also compare the
aliasing probability and fault coverage of Multiple Input Shift
Register (MISR) and Modular Addition Signature Analyzer (MASA)
by software simulation. The simulation data show that MISR is
better than MASA. We propose a modified MASA which is shown to
have a better fault coverage than MISR. However, by Markov
chain process technique modified version is shown to have
aliasing probability dependent on the bit error rate of the
error vector because its transition matrix is not doubly
stochastic. This indicates that MASA is a good signature
analyzer for a certain class of application which is still
under investigation. According to the simulation results, we
adopt the Linear Feedback Shift Register (LFSR) based Build-In
Self-Test (BIST) in BS-BIST generator which is implemented as
an optional structure.
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